1. Field of the Invention
The present invention relates to the field of semiconductor testing systems; more particularly, the present invention relates to compensating for inaccuracies of stimulus (test) signals as seen by the semiconductor device under test (DUT).
2. Related Art
The goal of semiconductor, or integrated circuit (IC), testing is to determine whether an IC meets its functional design specification. Functional testing consists of applying a number of electronic test signals to the input pins of an IC and measuring the resulting signals on its output pins. Each test signal consists of a test pattern created by a test pattern generator to simulate the system environment in which the IC is intended to operate. A test signal generator controls the speed and the time at which each test signal is applied to the IC pins, and enables timing measurements of the output signals. These signals and their timing are generated by pattern data and timing marker values. The signal amplitude level of these test signals must be able to change to meet the requirements of the semiconductor device family, i.e., ECL, TTL, etc. As such, each electronic test signal is derived from a set of digital timing values and a set of digital amplitude values. Modern semiconductor test systems typically have six timing marker values to generate all different timing waveforms and as many as seven reference analog levels for controlling signal amplitude and current requirements. The timing and amplitude values are programmed by the system operator.
FIG. 1 illustrates a prior art testing system. Referring to FIG. 1, the testing system includes a tester controller 111 and a tester mainframe 110. The tester controller 111 typically comprises a personal computer or work station. As shown, for purposes of explanation, the tester controller 111 comprises a central processing unit (CPU) 111A coupled to a disk memory 111B via a bus. The tester mainframe 110 comprises a timing generator 120 having timing and level registers, such as timing register 131 and level register 132. Pin electronics 130 are coupled to the timing and level registers in the test signal generator 120 and are also coupled to the device under test (DUT). When operating, the CPU 111A runs a program that sends programmed timing and amplitude values to the tester mainframe 110 for storage in timing registers, upon which the test signals are generated and driven to the DUT using pin electronics 130 in a manner well-known in the art.
Each test signal is characterized by its timing and its amplitude. With respect to the timing, the test signal is supposed to be at a particular state at a particular time. One problem in prior art systems is that by the time the test signals arrive at the device under test (DUT), their timing may not be accurate due to signal propagation through many electronic circuits and cables in the testing system (e.g., in the tester mainframe). The edge of the test signal is an indication of when the signal arrives. A test signal may arrive too early to the DUT when the edge of the signal rises too quickly (i.e., the slope of the edge is steep). On the other hand, a test signal may arrive too late to the DUT when the edge rises too slowly (i.e., the slope of the edge is shallow). A fraction of a microsecond too early or too late may affect the results of testing, and thus affect the yield, because the DUT would not receive the test signals at the correct time and would fail to function correctly. In other words, devices that operate correctly may be rejected due to inaccurate test signals.
The problem of timing accuracy of test signals in prior art semiconductor testing systems is compounded by the non-linearity of the test signals. As discussed above, the test signals are generated from programmed timing and amplitude values. Ideally, the tester should be able to output a test signal that matches its programmed value. For instance, if a signal is programmed to be 5 volts, the signal produced by the tester at the input of the DUT should be 5 volts. However, prior art semiconductor test systems do not have a perfectly linear response to the programmed values. That is, the actual amplitude of the resulting test signal may not be at the programmed level.
In the prior art, to compensate for timing inaccuracies due to unequal electrical cable length and the non-linear response of the testing circuitry, calibration is performed. To correct for amplitude inaccuracies, an offset and a gain factor are applied to programmed amplitude values. Using the offset, a test signal having a zero volt amplitude is generated by a programmed value of zero volts. Even though the offset adjusts the amplitude to ensure a programmed value of zero volts, a gain factor may also be required to adjust the linear response of the system for other programmed voltage values. The gain factor, which may be either positive or negative, compensates for the specific voltage offset for an individual test signal so as to adjust the system response to be as close to linear as possible (i.e., a programmed value of 1 volt results in a test signal amplitude of 1 volt, a programmed value of 2 volts results in a test signal amplitude of 2 volts, etc.). There may be more than one gain factor.
In prior art semiconductor test systems, level and timing calibrations are performed through calibration software to compensate for test signal inaccuracies. The calibration software resides and runs in the tester controller. During calibration, the tester controller sends a predefined set of programmed values to the tester mainframe 110, which generates timing signals. Well-known comparison circuitry (not shown) is coupled to the pin electronics 130 to measure the test signals that are generated. The calibration software determines the differences between the programmed and measured timing and level values of each test signal, and stores them in a table in a general purpose memory such as disk file 111B. Then, based on these differences, the calibration software adjusts the amplitude and timing of the test signals by adjusting the programmed values. For instance, the calibration software may apply (add or subtract) an amplitude offset to the test signal and also multiply the amplitude of the test signal by the gain factor. The arithmetic operations are performed by the CPU (e.g., CPU 111A) of the tester controller. Thus, all of the adjustments to the programmed values are made under the control of the tester controller.
A problem with software calibration systems is that for every input signal, its programmed value must be read and then compensated by the CPU. The CPU must access the table of compensation values in the disk file, locate and obtain the compensation factor(s) from the table, and then perform all of the necessary arithmetic operations. Thus, the disk file must be accessed for each programmed value prior to setting up test system registers. The disk accesses are slow, causing the generation of test signals with the desired timing and amplitude to be slowed as well. Also the CPU of the tester controller is required to perform all of the compensation while being responsible for generating test patterns as well. In applications where a large number of test signals need to be applied to the input pins of the DUT because of, for instance, device characterization, schmoo (varying at least one parameter to see device behavior, e.g., varying the power supply voltage to see how the device is functioning in response to the adjustment), etc., there would be a large time overhead before testing can begin as each programmed value undergoes the correction process. It would be desirable to compensate programmed values used to generate test signals while avoiding the overhead and the problems associated with the prior art software calibration.